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Altera_Forum's avatar
Altera_Forum
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12 years ago

Using sensitivity list for always block

Hello, I am just having a small confusion regarding best usages of sensitivity list. I understand that for combinational logic synthesis, all the signals should be included in the list (always @ (*))...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi rbugalho (http://www.alteraforum.com/forum/member.php?u=27812), yes, my signal is generated by synchronous logic. I had the intuition that it might not be a good idea and hence decided to do the following..

always @ (posedge clk) begin

if (mysignal == 1)

//do stuff

end

I hope the above is fine. Can you please elaborate how it complicates the design ?