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Altera_Forum's avatar
Altera_Forum
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12 years ago

Using sensitivity list for always block

Hello, I am just having a small confusion regarding best usages of sensitivity list. I understand that for combinational logic synthesis, all the signals should be included in the list (always @ (*))...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

yes it is. You are essentially making a new clock out of logic, and thats not a good idea, as it can cause timing problems. Just stick with a single clock and use clock enables:

always @(posedge clk)

if en = 1

//do something