Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHi Daniel,
I am not very sure how to answer your question but I will try with my limited exp. I was thinking that I can use the SDRAM Controller provided in the Quartus and write a user logic which will act as a master to the avalon bus and the SDRAM Controller will be connected to the slave and I can generate the necessary signals. Please let me know if it can work like this. also I want to include the nios processor in the design, so basically I have nios and User Logic as master to the avalon bus and SDRAM controller is connected as slave. Please advice Thanks, sony