using SDC_STATEMENT

I am trying to embed sdc statements into verilog but am having no success. I have found a couple of forum posts on this but they don't seem to shed any light on the matter, plus I can't find any documentation on Alteras web site.

I have added the line below to my verilog design but it doesn't have any effect (as if I had it in the main sdc file). Can anyone help?

(* ALTERA_ATTRIBUTE = "-name SDC_STATEMENT set_max_delay 2 -from  -to "*)

Thanks in advance,

Richard