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Honored Contributor

12 years ago

Using PLL "lock" signal as the async reset in Verilog

If I want to use the PLL "lock' signal to work as an async reset, the "lock" signal will keep low after the FPGA is powered and goes high after a duration. If I won't reset my PLL, then it means "loc...

Altera_Forum

Honored Contributor

9 years ago

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This is synthesizeable - it tells the compiler what the initial register state is in the download bit-stream.

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Would this be the 'initial' block?? Or is there something else?

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Using PLL "lock" signal as the async reset in Verilog

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