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Honored Contributor
Honored ContributorUsing PLL "lock" signal as the async reset in Verilog
If I want to use the PLL "lock' signal to work as an async reset, the "lock" signal will keep low after the FPGA is powered and goes high after a duration. If I won't reset my PLL, then it means "loc...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- This is synthesizeable - it tells the compiler what the initial register state is in the download bit-stream. --- Quote End --- Would this be the 'initial' block?? Or is there something else?
