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Altera_Forum
Honored Contributor
Honored ContributorUsing PLL "lock" signal as the async reset in Verilog
If I want to use the PLL "lock' signal to work as an async reset, the "lock" signal will keep low after the FPGA is powered and goes high after a duration. If I won't reset my PLL, then it means "loc...
Altera_ForumHonored Contributor
Honored ContributorI also have the question about initial value for signal in VHDL.
As you mentioned " signal q : std_logic := '0'; -- power-on condition ". Is this command synthesisable which make the signal q be "0" after power (don't need to do reset)? Or is this just for simulation? Thanks.
