Forum Discussion
Steve-Mowbray-ENL
Occasional Contributor
10 months agoUsing PCIe HIP core clock out to drive IOPLL reference clock -- advise on set_false_path syntax
Hi Need advise on suitable set_false_path design constraint construction for the following scenario where PCIE HIP core clock out is used as the reference for an IOPLL instance: Impact of doi...
- 10 months ago
Hi FvM
So it seems when the base/parent clock for the 100MHz domain was the external crystal Quartus was treating it as an unrelated clock hence no timing failures and status/control bits between the clock domains have synchroniser depth of 2 -- when PCIe core clock out was substituted for the external crystal -- Quartus started treating both clocks as related even though decoupled using an IOPLL instance -- the following design constraints appear to correct the situation
set_false_path -from [get_clocks {u0|pcie_hip|coreclkout}] -to [get_clocks {u0|iopll_1|*}] set_false_path -from [get_clocks {u0|iopll_1|*}] -to [get_clocks {u0|pcie_hip|coreclkout}]Thanks
Steve
FvM
Super Contributor
10 months agoHi,
false path for clock makes no sense. You want to find out why you get timing failure in your design, which data pathes are causing it and how it can be handled correctly. False path is only appropriate if respective timing is actually don't care. Unsubstantiated false path causes most likely data corruption.
I guess you have domain crossing data path between 125 and 100 MHz clock domain causing timing violation. If so, you need to use synchronizer to transfer data consistently.
false path for clock makes no sense. You want to find out why you get timing failure in your design, which data pathes are causing it and how it can be handled correctly. False path is only appropriate if respective timing is actually don't care. Unsubstantiated false path causes most likely data corruption.
I guess you have domain crossing data path between 125 and 100 MHz clock domain causing timing violation. If so, you need to use synchronizer to transfer data consistently.