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Altera_Forum
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8 years ago

Using new Quartus (17.0) with Stratix III

Hi, I hope I'm at the right place. I got a Stratix III to run a control of an electrical converter. The usage of the FPGA is arround 40%. Because newer versions of Quartus II are not suppor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Did you have a full pinout and time specs? How full is the stratix 3? How full is the stratix 5? Many things affect compile time, not just the tool version. Tool version usually has a small effect. The biggest effect will be how full the device is and how tight the timing constraints are. Given the 5 is much larger than the 3, your design probably uses only a small %of the device resources of a device using a much faster technology.