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Could anybody explain to me what I'm doing wrong? What's the proper way to instantiate the provided BFMs functions in VHDL testbenches?
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I haven't tried using the VHDL BFMs, but in my experience, Altera's msim_setup.tcl scripts suck.
1. Look in msim_setup.tcl
msim_setup.tcl suckiness#1: Altera names the library it compiles the HDL component into after its Qsys name. This is stupid, since if I have a Qsys design with three component instances, then I end up with three separately named libraries.
Are the packages you are trying to use actually getting compiled into the libraries you are referencing? If not edit msim_setup.tcl to reflect the libraries you want to use. This solution is annoying, since you need to edit msim_setup.tcl each time you regenerate the Qsys system.
2. Default bindings
Its quite possible that you could exploit a Verilog feature of Modelsim to work around what may be an issue with. The vsim -L option can be used to tell Modelsim which libraries to search for default bindings. As long as your HDL code has a component declaration, then the component should resolve to the last instance compiled (which is in one of the libraries referenced by -L).
If none of these ideas pan out, try and post a minimal set of code, along with a text file of what you are trying to do, and I'll take a look.
I posted a SystemVerilog design that uses the BFM master and slave here (see Post#25);
http://www.alteraforum.com/forum/showthread.php?t=32952&page=3 Read through that and perhaps that has a solution too, eg., you could create your simple design in Verilog, and then again in VHDL. It should be possible to get the same functionality working with either language.
Note: as far as HDL languages go, I'm more familiar with VHDL. The reason I wrote the BFM test in SystemVerilog is that the VHDL BFM is only a recent addition to the test suite.
Cheers,
Dave
Honored Contributor
