Forum Discussion
Altera_Forum
Honored Contributor
9 years agoyou would have a counter free running, and then use the counter to generate a clock enable:
for example - to divide a clock by 16 - eg in VHDL:
signal counter : unsigned(3 downto 0);
signal clk_en : std_logic;
process(clk)
begin
if rising_edge(clk) then
counter <= counter + 1;
if counter = 0 then
clk_en <= '1';
else
clk_en <= '0'
end if;
if clk_en = '1' then
-- logic here is only switched on every 16 clocks
end if;
end if
end process;