Honored ContributorI need to stop and up/down counter (implemented using LPM_COUNTER) from overflowing. The documentation doesn't really describe the behaviour of the carry out port, so can anyone tell me if ANDing the carry out in to the cnt_en input will do this for me? I'm worried that it will lock up at max or zero even when I change direction to count away from the overflow.
Honored ContributorWell you can always factor in the direction input i.e. allow it to count away from max or min but not wrap in either direction.
Honored Contributorbtw cout is the AND of all the counter bits so it can be used to disable counting as you describe. If you're not sure try simulating it. Alternatively add a bit of logic to detect your own min and max "terminal" states in each direction.
Honored ContributorThose suggestions are sensible and had occured to me, but I rather wish the documentation told me what I need to know. When you say that cout is the AND of all the bits, how do you know this. I assume that's when counting up, and it's the NOR of all the bits when counting down?
Honored ContributorWell it comes from a knowledge of how counters work. If you've ever had the pleasure of working with 74 series logic devices like the 74LS163 for example you would probably know. But I agree it isn't actually very clear from the description.
Think about a 3 bit counter. How would you design one with D type flip flops? Try to do it on paper and you will see. 000 001 -> carry into bit 1 010 011 -> carry into bit 1 and 2 100 101 -> carry into bit 1 110 111 -> carry into bit 1, 2 and 3 (if bit 3 added separately, but this is a 3 bit counter)Honored ContributorIs there any reason you have to use LPM_COUNTER? cant you just use some simple HDL?
Honored ContributorThanks for your input. I don't use HDL because I'm not very good at it and I'm assuming the LPM blocks will be optimised.
Honored Contributorthe synthesisor can infer LPM blocks from HDL code. and for things like counter they are so basic there isnt really much to optimise.
Honored ContributorPlus HDL has the advantage that you can simulate it.
Honored ContributorFair point about the optimisation, but as I'm not very good at HDL I'm also not very good at simulating it.
Honored ContributorNo better time to learn :)
You can isntantiate all the LPM modules directly in HDL if you want anyway.
