Honored ContributorI need to stop and up/down counter (implemented using LPM_COUNTER) from overflowing. The documentation doesn't really describe the behaviour of the carry out port, so can anyone tell me if ANDing the carry out in to the cnt_en input will do this for me? I'm worried that it will lock up at max or zero even when I change direction to count away from the overflow.
Honored ContributorTime to learn, that will be the day :(
The proposal went something like this: Client - We'd like you to update a design you worked on 9 years ago. Me - Who is going to do the FPGA as it's not my area of expertise? Client - We don't want to work with that guy any more, you'll have to do it. Me - But it really isn't my area of expertise. Client - Well do the best you can, I'm sure you can manage it. It's nice that people have confidence in me, but it was always going to be tough.Honored ContributorAssuming you're working on a design that was implemented using schematic, you can mix HDL and schematic.
You just need to write a module that does what you need, then have Quartus create a symbol for it and you can use it in your schematic.
