Using LCELL as a delay

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Arbitrarily placed logic cells or functionless gates will be usually removed in synthesis, unless you assign respective keep synthesis attributes to the signal. There are various Altera forum threads discussing techniques of logic cell delays, also the Altera advanced synthesis cookbook refers to it.

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LCELL by 'default' within quartus is an exception. This will force quartus, even though there is no logic other than passing straight data thru, to use a logic cell as in kito's example block diagram.

Kito, remember, you must always assume the added delay you get will be as short as the fastest possible feed-thru delay of 1 logic cell withe the fastest possible fitting, to, anytime longer each time you compile & fit. There will also be additional error due to die performance, ambient temperature, and, core supply voltage.

As for using a clocked d-flipflop, have you considered inverting the clock just for that 1 d-flipflop. Also, if your clock is below 100Mhz and you have a free PLL, you can feed that 1 d-flipflop at double or more frequency...