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Altera_Forum
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14 years ago

Using LCELL as a delay

Hi, I implemented a LCELL to add a delay to a tristate function for a bidir pin. This buffer is a output pin on the device. I wanted to add a delay because a glitch occurs when the IO switche...
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Altera_Forum
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14 years ago

Arbitrarily placed logic cells or functionless gates will be usually removed in synthesis, unless you assign respective keep synthesis attributes to the signal. There are various Altera forum threads discussing techniques of logic cell delays, also the Altera advanced synthesis cookbook refers to it.