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Altera_Forum's avatar
Altera_Forum
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14 years ago

Using LCELL as a delay

Hi,

I implemented a LCELL to add a delay to a tristate function for a bidir pin. This buffer is a output pin on the device. I wanted to add a delay because a glitch occurs when the IO switched from an input to an output. The data from the previous clock cycle shows up as a glitch until the correct data propagates to the IO buffer. I use an AND gate to add more delay when IO makes a 0=>1 transition and minimal delay during 1=>0 transition.

I understand that using LCELL as delay element is not good practice, but I wasn't really sure how else to implement this.

I also would prefer not to waste a clock cycle by pre drive the IO buffer and burn up a clock cycle.

Thanks for any help.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Arbitrarily placed logic cells or functionless gates will be usually removed in synthesis, unless you assign respective keep synthesis attributes to the signal. There are various Altera forum threads discussing techniques of logic cell delays, also the Altera advanced synthesis cookbook refers to it.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I actually already implemented an LCELL delay in my IO path and it works. I also read in the forums its not a good way to do this because of PVT variation. So I was just wondering if people had better techniques. For example, do people use sdc to control IO path delay? I recently added sdc constraints to minimize skew however I suppose I can play around with using the sdc to minimize path delay of the tristate signal.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    So I was just wondering if people had better techniques.

    --- Quote End ---

    PVT variations occur by nature of logic cell and routing delays and don't depend on how they are implemented in your design. Using timing constraints for it has the advantage, that the effect of PVT variations is already checked in timing analysis.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    But how to use the timing constraints to delay the time? can you make an example?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Arbitrarily placed logic cells or functionless gates will be usually removed in synthesis, unless you assign respective keep synthesis attributes to the signal. There are various Altera forum threads discussing techniques of logic cell delays, also the Altera advanced synthesis cookbook refers to it.

    --- Quote End ---

    LCELL by 'default' within quartus is an exception. This will force quartus, even though there is no logic other than passing straight data thru, to use a logic cell as in kito's example block diagram.

    Kito, remember, you must always assume the added delay you get will be as short as the fastest possible feed-thru delay of 1 logic cell withe the fastest possible fitting, to, anytime longer each time you compile & fit. There will also be additional error due to die performance, ambient temperature, and, core supply voltage.

    As for using a clocked d-flipflop, have you considered inverting the clock just for that 1 d-flipflop. Also, if your clock is below 100Mhz and you have a free PLL, you can feed that 1 d-flipflop at double or more frequency...