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the voltage range you mentioned is the analogue side of ADC. The digital values could be +/-, see the ADC data sheet.
if ADC clock is 20MHz (and sampling rate is 20Msps) but system clock is 100MHz then your fft should tell if it supports time folding to reduce resource.
In any case the system clock and data clock must be synchronised or clock domains crossed safely(dc fifo).
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I think my purpose is decreasing fft process time, instead of saving resource. And i worry that which would affect the FFT result, could i get a result which is what i don't need?
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