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your fft ip should tell you. Normally ADC data that represents a signal swings around zero (no dc) if in 2's complement. But it could be using offset binary which needs inverting the sign bit.
At HDL level I expect std_logic_vector type.
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I see, maybe their analog signal just as you said around zero. however, the negative value is no sense for our system. so our system the signal is from 0~1000 mv, instead of -500~500 mV.
BTW, i have another question need you guidance: the ADC sample clock is 20 MHz, but my system clock is 100 MHz, do i synchronize the samples from 20 MHz into 100 MHz firstly(FFT run at 100 MHz, and i think this will save process time) or synchronize the FFT's out from 20 MHz to 100 MHz(FFT run at 20 MHz )? Which one is better for our application? Will each of above process affect the frequency spectrum analysis?
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