using constant

Before we gets into timing, you may want to verify its functionality. Does your design work in Functional Simulation? If yes, then we only can conclude it is a timing issues. Then later you set your timing contraint of your design and run Timing Analysis. If no timing violation occurs, then only try run Timing Simulation. If it fails, then we only start debugging from there. If timing contraints are set correctly, and functional simulation has been verified, and your stimulus are correct, most likely the Timing Simulation will pass unless your design contains a lot of asynchronous stuff.

Hi

This feels like a problem I had with Quartus changing my state machines. Without seeing more of your code, if this could be a cause, you could change the anal & synthesis setting for state machines to one hot. The Quartus manual says it encodes VHDL one-hot by default. I have in the past used code such as Quartus handbook volume 1 page 8-38, example 8-25, for applications like what yours looks like. And, the VHDL attribute keep may do the trick for you.

Randall,