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Altera_Forum's avatar
Altera_Forum
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19 years ago

using constant

Hi...

Have a question (hope that not 2 stupid)

I defind

constant ram1 : std_logic_vector (2 downto 0) :="001"; -- only RAM1

constant ram2 : std_logic_vector (2 downto 0) :="010"; -- only RAM2

constant ram3 : std_logic_vector (2 downto 0) :="100"; -- only RAM3

ram_indication= ram1 or ram2 or ram3.... (gets one of this)

I run timing simulation with *.vho and *.sdo

and got X00 X01 X11 ........ (instead of my values "001"...)

Is there any attribute I didn't use?

Its really not easy to cope with timing simulation...

Thank you

ari

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Before we gets into timing, you may want to verify its functionality. Does your design work in Functional Simulation? If yes, then we only can conclude it is a timing issues. Then later you set your timing contraint of your design and run Timing Analysis. If no timing violation occurs, then only try run Timing Simulation. If it fails, then we only start debugging from there. If timing contraints are set correctly, and functional simulation has been verified, and your stimulus are correct, most likely the Timing Simulation will pass unless your design contains a lot of asynchronous stuff.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Hi

    I just asked about timing simulation...

    of course it works in functional simulation!!!

    I know all the theory you wrote and just asked about the constant values...

    ari
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    This feels like a problem I had with Quartus changing my state machines. Without seeing more of your code, if this could be a cause, you could change the anal & synthesis setting for state machines to one hot. The Quartus manual says it encodes VHDL one-hot by default. I have in the past used code such as Quartus handbook volume 1 page 8-38, example 8-25, for applications like what yours looks like. And, the VHDL attribute keep may do the trick for you.

    If this is unrelated to a state machine, take a look at more of the surrounding code to see why Quartus would optimize the way it did.