Honored Contributor
Honored ContributorThis feels like a problem I had with Quartus changing my state machines. Without seeing more of your code, if this could be a cause, you could change the anal & synthesis setting for state machines to one hot. The Quartus manual says it encodes VHDL one-hot by default. I have in the past used code such as Quartus handbook volume 1 page 8-38, example 8-25, for applications like what yours looks like. And, the VHDL attribute keep may do the trick for you.
If this is unrelated to a state machine, take a look at more of the surrounding code to see why Quartus would optimize the way it did.
