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I see what you meant now.
1. In your screenshot, the launch edge is sperated from the latching edge even they are the same clock.
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I think pletz is mixing up setup with hold relationship.
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2. In your screenshot, the clock delays for the two edges are the same, while the clock delays in my screenshot have a difference of 0.775ns.
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That's exactly the problem, your clock skew is too big.
It would be useful to see a TimeQuest report with the clock path for both registers. Is this an external clock? How it is constrained?
Double check the clock is global. But this doesn't seem to be the problem, because even with non-global routing the skew shouldn't be that big for LABs that are almost adjacent.
You have lots of warning about unconstrained clocks. Not sure if this has any relation to the problem, but it might be worth to check them.
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