--- Quote Start ---
Hi,
no idea what happend ???:confused:
--- Quote End ---
I see what you meant now.
1. In your screenshot, the launch edge is sperated from the latching edge even they are the same clock.
2. In your screenshot, the clock delays for the two edges are the same, while the clock delays in my screenshot have a difference of 0.775ns.
And I think you are right that the 0.775ns skew is the cause of the hold time violation. But, does anyone know where I should look for the cause of the skew?
BTW, my screenshot is in post# 12 up there and pletz's screenshot is in post# 17.
Appreciated!
Hua
Honored Contributor
