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The clk_7m is a generated clock but defined as a global signal.
Clock skew? could you please point me to where you find it?
launch and latch on the same edge? correct me if I am wrong but, I thought it's the way the timequest timing analyzer present the waveform. The source sends new data at the launch clock edge, at the same edge the receiver latches the old data from the last clock cycle. In the screenshot I posted it seem that the data arrived at the receiver end too soon. But why is the real clock delay is so much shorter than the expected clock delay?
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Hi,
clock skew means that you have different delays for the clock path to the launch and latch register. When the clock is distributed over a global net and the registers are placed in the same area of the FPGA the delay should be the same.
I have posted a timing diagramm where you can see what I would expect.
Kind regards
GPK
Honored Contributor
