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Hi
How does the clock paths looklike ?
Why are the launch and latch edge identical and where does the large clock skew (0.8 ns) comes from ? Is the clk7m defined as global ?
Kind regards
GPK
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The clk_7m is a generated clock but defined as a global signal.
Clock skew? could you please point me to where you find it?
launch and latch on the same edge? correct me if I am wrong but, I thought it's the way the timequest timing analyzer present the waveform. The source sends new data at the launch clock edge, at the same edge the receiver latches the old data from the last clock cycle. In the screenshot I posted it seem that the data arrived at the receiver end too soon. But why is the real clock delay is so much shorter than the expected clock delay?
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