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Altera_Forum
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16 years ago

Using both edges of a clock

Hi there, We have some old design modules from way back and being used in several products. The design is messy and doesn't have any documentation, making it quite time-consuming to rewrite and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Thanks guys. The hold time optimization settings were all checked using timing optimization advisor...

Here are two screen shots I took for the hold time violations I got in the latest compilation. Now the problem actually shifted to the rising edge of the clk (clk_7m). The timing report is also attached in the zip file.

Any clue from here?

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Hi

How does the clock paths looklike ?

Why are the launch and latch edge identical and where does the large clock skew (0.8 ns) comes from ? Is the clk7m defined as global ?

Kind regards

GPK