Using both edges of a clock

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The Technology Map Viewer should show correctly, how the inversion is implemented. As far as I remember, previous FPGA families didn't have a local clock inversion.

To understand the reason for timing violations, you can check what's between the registers.

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Thanks guys. The hold time optimization settings were all checked using timing optimization advisor...

Here are two screen shots I took for the hold time violations I got in the latest compilation. Now the problem actually shifted to the rising edge of the clk (clk_7m). The timing report is also attached in the zip file.

Any clue from here?