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How do I find out if that's the case? The failed data path is actually between two registers clocked by the inverted clock.
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It shouldn't happen in that case. I was thinking, since you mentioned it was a messy old design, that the clock was being manually inverted, or that some clock was being gated or derived. But this would affect only transfers from the original to the derived clock, not between two registers using the same clock.
There are a couple of fitter settings to optimize hold timing. But it might be better to check before, the timing analyzer reports. You might want to post relevant portions of the report here.
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It's an VHDL design. Are you suggesting that if I use something like "if clk'event and clk='0' then", QII should aumatically invert the clock locally in a LE? The design is actually written in that way....
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Yes. To be more precise, the inversion is performed at LAB level.
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