Using both edges of a clock

Thanks vjAlter.

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If for some reason the timing analyzer considers the inverted clock as a buffered non-inverted clock, it might report fake hold violations.

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How do I find out if that's the case? The failed data path is actually between two registers clocked by the inverted clock.

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There is no need to invert and route and inverted clock. All the registers in the device have a programable clock inversion. You only specify the usage of the opposite edge by using the corresponding HDL construct, such as negedge in Verilog.

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It's an VHDL design. Are you suggesting that if I use something like "if clk'event and clk='0' then", QII should aumatically invert the clock locally in a LE? The design is actually written in that way....