Using both edges of a clock

Using both edge of the clock should normally not produce hold violations (unless you mean setup violations).

The most common cause of hold violations is clock skew produced by a derived, gated or buffered clock.

I never tried to manually invert a clock, because usually is not needed (see below). If for some reason the timing analyzer considers the inverted clock as a buffered non-inverted clock, it might report fake hold violations.

There is no need to invert and route and inverted clock. All the registers in the device have a programable clock inversion. You only specify the usage of the opposite edge by using the corresponding HDL construct, such as negedge in Verilog.