Using both edges of a clock

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Hi there,

We have some old design modules from way back and being used in several products. The design is messy and doesn't have any documentation, making it quite time-consuming to rewrite and/or debug them. Sometimes we got hold time violations in the design and it is the most likely because the design uses both edges of clocks.

My questions are:

How does QII implement a design like this? Does QII automatically invert the clock and put both clocks (the one and the inverted one) on global networks? If it doesn't, is there an easy way to constraint the design?

Thanks,

Hua

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Hi,

how large and how many hold time violation do have in your design ?

Kind regards

GPK