New Contributor
New ContributorI've done this, (creating the qsys ip) but there is a complex automated script environment for the design and qsys components are rather troublesome to treat (need to update makefiles ...).
Furthermore the qsys ip, at its lower level generated a verilog file that uses the altera_syncram component and the number of the generic generic parameters is not identical to those of the altsyncram vhdl component ...
Super ContributorThere is still one more thing that you can try. Our Quartus tool has the full design template for true dual port in which you can just pop it into your project and use it right away.
Create a new .vhd file, right-click on the blank space to opens the context menu, scroll to Insert Template, then a window Insert Template will pop up, choose VHDL > Full Designs > RAMs and ROMs > True Dual Port RAM (single clock).
Hope it helps on your case.
New ContributorThank you for the help.
So what you suggest is an RTL implementation of the memory (e.g. not structural using the altsyncram function directly).
=================================
library ieee;
use ieee.std_logic_1164.all;
entity true_dual_port_ram_single_clock is
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
port
(
clk : in std_logic;
addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;
addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;
data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
we_a : in std_logic := '1';
we_b : in std_logic := '1';
q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end true_dual_port_ram_single_clock;
architecture rtl of true_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
-- Declare the RAM
shared variable ram : memory_t;
begin
-- Port A
process(clk)
begin
if(rising_edge(clk)) then
if(we_a = '1') then
ram(addr_a) := data_a;
end if;
q_a <= ram(addr_a);
end if;
end process;
-- Port B
process(clk)
begin
if(rising_edge(clk)) then
if(we_b = '1') then
ram(addr_b) := data_b;
end if;
q_b <= ram(addr_b);
end if;
end process;
end rtl;
=============================
The only problem with this approach is that you might not be able to customize input/output registers and modes of operation (but it is some sort of an alternative I guess).
