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Altera_Forum
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15 years ago

Useing the TimeQuest timing analysis to analyze the PLL

In the process of learining the TimeQuest timing analysis,I used the TimeQuest timing analysis to analyze the PLL,but there are some timing requirements not met,I don't know what went wrong.

There are two outputs from the PLL,the phase and frequency of C0 remain unchanged relative to the CLK,the clock multiply factor of the C1 is 2,and the phase of C1 is -63.The report setup summary shows that the C1's slack is negative,I think the PLL should be able to achieve that kind of design,maybe there is something wrong with me.

Is there anyone can help me?

thank you in advance!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Now I found that if I connect the c1 of PLL to the output pin directly,the timing requirement will not be met.But if I add some registers among them ,the timing requirement will bt met.Is there anyone know why this is it? 

    
create_clock -name {sysclk} -period 20.000 -waveform { 0.000 10.000 } 
 
derive_pll_clocks -create_base_clocks
 
set_input_delay -add_delay  -clock }]  2.000 
 
set_output_delay -add_delay  -clock }]  1.000 
 
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
 
set_multicycle_path -setup -end -from }] -to |datain DATA|datain DATA|datain DATA|datain DATA|datain DATA|datain DATA|datain DATA|datain}] 2

    thank you in advance!