Useing the TimeQuest timing analysis to analyze the PLL

Now I found that if I connect the c1 of PLL to the output pin directly,the timing requirement will not be met.But if I add some registers among them ,the timing requirement will bt met.Is there anyone know why this is it?

create_clock -name {sysclk} -period 20.000 -waveform { 0.000 10.000 } 
 
derive_pll_clocks -create_base_clocks
 
set_input_delay -add_delay  -clock }]  2.000 
 
set_output_delay -add_delay  -clock }]  1.000 
 
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
set_output_delay -add_delay  -clock }]  1.000 }]
 
set_multicycle_path -setup -end -from }] -to |datain DATA|datain DATA|datain DATA|datain DATA|datain DATA|datain DATA|datain DATA|datain}] 2