Unfortunately it's company code so I can't post, but the motivation behind all this is...
The design team regularly come to me with very small blocks that they are considering integrating into the main design. What the first question they ask is "will it time if we add it to the design". Now adding it to the design takes time and the builds themselves take hours so I need a quick and simple method to answer their question.
They way I did it this time is just build the small block on the full design device giving the tool free reign to do what it wants - I don't think this is the best way to do it as hence I'm now looking at build a 'small block' methodology based on previous suggestions (logic lock, double register and clock buffers etc).
So far I've adopted the 'virtual pins' script from the Altera web site for blocks with masses of I/O and I've also developed a generic constraints script.
Any suggestions welcome.