Useful clock skew

A clock skew of 3 ns, sounds high to me, for the same clock.

Usually the skew is a few hundred PS for clocks, unless something is breaking the the clock fanout such that the global clock buffers can not be used, so it's using standard routing resources.

If it's a small section of logic, you may try logic locking the logic in a small region of the FPGA.

If you have multiple clocks, you may try to force the critical clock to use the global clock networks.

You may want to look closer at the clock delay paths, and see if you have some gating or other logic in one path that isn't in the other. This could add to your skew issues.