Thanks for the reply.
Yes I expect some clock skew but I thought around 3ns was a little bit on the large side. Should I expect this much even for a small block when targeting a large Stratix IV device? Maybe the logic is spread out around the massive expanse of the device?
Is this the fitter/timer using deliberate useful clock skew?
If it is can I turn it off?
At the end of the day it's not the end of the world as it's just a case of picking out the data delay from the reports - just thought it would be useful to turn it off if I could.
I'll try your suggestion of double registering I/O - thanks.