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Altera_Forum's avatar
Altera_Forum
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16 years ago

use of 'path_name in if generate

I've defined some global signals in a package :-

signal TB_TESTPOINT_A : std_logic;

signal TB_TESTPOINT_B : std_logic;

signal TB_TESTPOINT_C : std_logic;

and I want to connect them down the hierarchy to point in my design. The module I'm connecting them to has several instantiations (3 in this example), and I want to connect a different test probe to each instantiation. I've tried :-

if local_signal'path_name = ":tb_top:uut:full_path:local_signal" generate

TB_TESTPOINT_A <= local_signal;

end generate;

however Modelsim Altera gives me this error :-

** Warning: module.vhd(256): (vcom-1148) Condition in IF GENERATE must be static.

If I use a generic in an if generate statement, that compiles OK but surely is not static at compile time, so why is 'path_name any different?

Any suggestions please?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    generic is a constant decided at compile time and so is static.

    The "generate" needs to decide once and for all at compile time whether to generate or not. It is not a design switch.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    One question? why are you connecting probes like this? modelsim gives full visibility of all signals.

    Also, Quartus will not compile global signals.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks both for responding so quickly! :)

    I am using these signals as probes in my testbench, so I can automatically detect whether the lower levels are doing the right thing. (I know I can see them in Modelsim anyway but I can't compare values without making them visible in the testbench itself). I won't be compiling the global signals into Quartus so it's not a problem that they are not supported there.

    I might not have been clear that I was talking about compiling the VHDL into Modelsim for simulation - not compiling into Quartus. My understanding is that when compiling VHDL for simulation, generics do not have to be fixed, however by the time the design is elaborated for simulation then of course they do. The simulator will then know whether to build the generate statement which depends on the generic or not.

    My question was, why is the 'path_name attribute treated differently from a generic? The warning message only appears for the attribute, not the generic. (Both do appear to work correctly in the simulation, however).