use of 'path_name in if generate

Thanks both for responding so quickly! :)

I am using these signals as probes in my testbench, so I can automatically detect whether the lower levels are doing the right thing. (I know I can see them in Modelsim anyway but I can't compare values without making them visible in the testbench itself). I won't be compiling the global signals into Quartus so it's not a problem that they are not supported there.

I might not have been clear that I was talking about compiling the VHDL into Modelsim for simulation - not compiling into Quartus. My understanding is that when compiling VHDL for simulation, generics do not have to be fixed, however by the time the design is elaborated for simulation then of course they do. The simulator will then know whether to build the generate statement which depends on the generic or not.

My question was, why is the 'path_name attribute treated differently from a generic? The warning message only appears for the attribute, not the generic. (Both do appear to work correctly in the simulation, however).