you can convert std_logic_vector into signed or unsigned:
my_us <= unsigned(my_input)
but you could just declare my_input as unsigned in the first place (it means you have less type conversion)
but if you really insist on keeping std_logic_vector:
op <= std_logic_vector(unsigned(a) * unsigned(b) );
the same for signed.
std_logic_vector, signed and unsigned are basically all of the same type - an array of bits. But the numeric_std package defines arithmatic functions for signed and unsigned.
I highly suggest you look for a VHDL tutorial. Altera provides them for free:
http://www.altera.co.uk/education/training/courses/ohdl1110