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why are you now using a generate loop? you're trying to create 4 multipliers.
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I haven't use a component before.. so i see an example in a book that use lpm.lpmmult to multiplie std_logic_vector.. so my input is std_logic_vector so i use this (component?! i think that generate.. generate components? is it ok?)
so can you tell me how can multiply two std_logic_vector without this lpm.lpm_mult..
with signed or unsigned there isn't this problem... so I wouldn't have written..
my input must be std_logic_vector and my outoput too.
So i haven't the knoledge of a designer of fpga because i'm only a student.. but if you want help me tell me how can resolve my problem..
I must realiza a state machine
in the first state(prodotto) i must do this operation pden=a*y and pnum=b*x, where a e b are costants of std_logic vector and x an input of std_logic_vector
in the second state (somma) i must sum these y= pden+pnum...
So.. the multipliers are only two...!
I think that there is a possibility to pass argoment to a component out of the process and use this at the second moment (second clock) in my process.
If you have same ideas.. thank!:o
by enrico
Honored Contributor
