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Altera_Forum
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13 years ago

Use Multicycle path for delayed wr enabled clk?

I have a design that uses a write signal enabled for one clock cycle, but delayed several clock cycles after the data that I'm writing is valid. So, lets say that the data is valid at the first risin...
Altera_Forum's avatar
Altera_Forum
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13 years ago

It's still all on the same clock domain. If I understand correctly, you want a multicycle of 3, to say the data has been available for 3 clock cycles:

set_multicycle_path -from <> -to <> -setup 3

set_multicycle_path -from <> -to <> -hold 2

So if your clock were 10ns, it would normally have a setup relationship of 10ns and hold of 0ns. These multicycles would make the setup 30ns and keep the hold at 0ns. This would buy slack on whatever path you specify in the -from/-to.