Use correct latch timing during place and route optimisation

Here is a simple example.

I created a circuit where data goes from a negedge flipflop, to a negative (open-low), level-sensitive latch, to a posedge flipflop.

In the timing analyser you can see that the setup time from the negedge flipflop to the negative (open-low), level-sensitive latch is as good as nothing. I expect that the setup time should be a bit less than half the clock period. Even with the "-dynamic_borrow" option I don't see anything change which I found strange.

Can you explain this?

This could have a lot of impact on the rest of the timing when the tool tries to fix this with clock skewing