New Contributor
Super ContributorWe do not receive any response from you in the email. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
New ContributorHere is a simple example.
I created a circuit where data goes from a negedge flipflop, to a negative (open-low), level-sensitive latch, to a posedge flipflop.
In the timing analyser you can see that the setup time from the negedge flipflop to the negative (open-low), level-sensitive latch is as good as nothing. I expect that the setup time should be a bit less than half the clock period. Even with the "-dynamic_borrow" option I don't see anything change which I found strange.
Can you explain this?
This could have a lot of impact on the rest of the timing when the tool tries to fix this with clock skewing
New ContributorDid you already have time to look into this?
