Forum Discussion
You may take a look at:
https://www.intel.com/content/www/us/en/programmable/documentation/psq1513989797346.html -> 1.1.10.2. Time Borrowing with Latches
The way to solve it is by: set_max_time_borrow 3 [get_registers lat*]
- Fromhell7775 years ago
New Contributor
I haven't tried this yet but when reading the documentation I did not think this would do anything.
It states that "the time borrowing never exceeds the maximum borrow value. However, you can specify a smaller maximum borrow time with the set_max_time_borrow SDC constraint."
And before this it is said that "the Timing Analyzer automatically computes the maximum amount of time borrowing available for each latch. Typically, the maximum amount of time borrowing available is roughly equivalent to half the clock period."
So this means that by default around half the clock period is taken as borrow time and it could be further constraint with the SDC command.
It does not state that this setting will enable correct borrow time calculation during place and route timing optimisations as is clearly said in the beginning of this section: "Implementation of latch time borrowing requires that you enable Dynamic borrowing mode (update_timing_netlist -dynamic_borrow). Otherwise, the Timing Analyzer calculates zero time borrowing for latches
So when reading this paragraph I interpret it as ignoring all borrow time unless you use update_timing_netlist -dynamic_borrow (also the set_max_time_borrow SDC command would then have no effect because the maximum borrow time is zero)
- Fromhell7775 years ago
New Contributor
I tested it by redoing the timing analysis after synthesis with the set_max_time_borrow option and it only made the timing violations worse