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Altera_Forum
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16 years ago

Use “don’t care” statement in vhdl code

I will use don’t care statements in my vhdl code. Quartus 2 have more degree of freedom to reduce logic. Example: Case aaa IS When 1 => bbb <= 1; When 2 => bbb <= 2...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Quartus will pick up Dont cares, but probably just ignore them, the same way it ignores 'X' statements.

For simulation purposes, it can be useful to specifially produce 'X's, like this example: 


if en = '1' then
  q <= d;
elsif en = '0' then
  null;  --hold q
else  --catch all for unitialised input enable
  q <= 'X';
end if;

With this example, you can see that inputs are uninitialised just by looking at the output. When quartus gets hold of it it strips out the else case and just puts in a DFFE.