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Altera_Forum
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16 years ago

Use “don’t care” statement in vhdl code

I will use don’t care statements in my vhdl code. Quartus 2 have more degree of freedom to reduce logic. Example: Case aaa IS When 1 => bbb <= 1; When 2 => bbb <= 2...
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Altera_Forum
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16 years ago

Overall, I think its probably safer just not to use dont cares. I dont think its really going to help the synthesiser optimise things in any meaningful way. But by all means give it a go and see if it makes any difference.