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Altera_Forum
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16 years ago

Use “don’t care” statement in vhdl code

I will use don’t care statements in my vhdl code. Quartus 2 have more degree of freedom to reduce logic. Example: Case aaa IS When 1 => bbb <= 1; When 2 => bbb <= 2...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for your answer,

I know that I must be carefully with don’t cares. But if Quartus detect the higher degree of freedom so the can it better optimize.

Detect Quartus the higher degree of freedom and can it with the help of this better optimize?