Dave,
I am not exactly sure which device is being used (FT2232 or FT232R for example) but many of the Terasic boards are FTDI controller + Max II CPLD for the on board USB blaster. Interestingly enough, the schematics for the DE-Nano, for example, do not show the circuit in schematic detail. Only a higher level block diagram is shown. From what I have looked at on the Terasic dev boards, this is generally true, as well as the recent and new Altera dev boards.
The frustrating part to me is the lack of transparency with a proven solution for this approach. I know, there have been several discussions of writing drivers, etc. on the forum, but the fact that this is not an "easy" process is a bit disappointing. So if Altera is going to discontinue the USB blaster, then as the pendulum swings this way, I would like to see more transparency on this driver and on board JTAG hardware.
The closest thing that I've seen to a really nice driver is something written in Python, which will program the Altera FPGA through JTAG, obtained at:
https://github.com/progranism/ft232r-jtag Maybe a group project to take the code and wrap a PyQt/PySide gui around the code that I just referenced with the previous link?
Thanks, James
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Hi James,
Which boards have you seen that use the FT2232? I've only ever seen the BeMicro use it. The "Arrow USB-Blaster" is significantly slower than a standard USB-Blaster when working with SignalTap II. I have a BeMicro and BeMicro-SDK interfaced to external FTDI UM245R and UM232H modules, and SignalTap II capture using the BeMicro is way slower than using the BeMicro-SDK. The FT2232C MPSSE mode can be operated at the same frequency as the bit-mode/byte-modes on the standard USB-Blaster, so I'm not sure what causes the speed difference ... probably software/driver support.
I've seen that some of the newer development kits now come with a USB-Blaster II = Cypress EZ-USB FX2 + MAX II. This implements a USB-Blaster plus a higher-speed comms channel to the on-board FPGA.
Cheers,
Dave
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