Honored Contributor
Honored ContributorHello, i've been away for a while because i had to attend a conference. Really, i'm very grateful for ur assistance.
I did exactly as u told me and i think it made some sense when i implemented. But the device (Stratix iii) output did not behave as expected (+++ this is the first time i'm using the device). So i decided to implement a simple logic(AND gate) and from my observation, apart from LED (LEDR(7)) that was assigned for output another LED (LEDR(4)) would come on alongside. In addition the 2-input AND gate seems to behave like a NAND, two HIGH = "no output", HIGH and LOW = "output", two LOW = "output". (note that "output" is shown at the assigned LED and another LED comes up alongside). But when "no output" none of them come up. Any help on this pls? Compiler warning shows "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details". --- Quote Start --- If "proposed.vhd" is your top level file then your gain signal has been mapped to FPGA pins. Just set those pins to the threshold value that you want. If you want a fixed value for your comparator, then you can always connect the B port to a constant signal instead of "gain" when you instantiate the comparator. --- Quote End ---
