Urgent VHDL Comparator

You moved the data assignment before the begin. You aren't allowed to do that, all the signal or variables assignments must be done after "begin".

But why are you using a "data" signal to begin with? You can directly compare A and B in your process. Besides, using the intermediary "data" signal in your process while it isn't on the sensitivity list will give you unwanted behaviour in a VHDL simulator.

And I agree with mmTsuchi, using ieee_logic_unsigned can be dangerous, you should stick to numeric_std instead and use its "unsigned" and "signed" types instead of std_logic_vector when they represent numbers.