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Honored Contributor[URGENT] Need helps !!
Hi. I need to solve my problem in this case.
Please pardon my variable name because it is in Indonesian. And i want to ask, how about the syntax about If inside If, different than else if. Here is my code :LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY Traffic IS
PORT (
clock : INSTD_LOGIC;
mode : INSTD_LOGIC;
darurat : INSTD_LOGIC;
M_US : OUTSTD_LOGIC;
M_BT : OUTSTD_LOGIC;
K_US : OUTSTD_LOGIC;
K_BT : OUTSTD_LOGIC;
H_US : OUTSTD_LOGIC;
H_BT : OUTSTD_LOGIC
);
END Traffic;
ARCHITECTURE behavioral OF Traffic IS
TYPE executionStage IS (s1,s2,s3,s4);
SIGNAL currentstate : executionStage := s1;
BEGIN
PROCESS(clock,mode,darurat)
variable ctime : integer := 0;
variable clk : integer := 0;
variable wkt_darurat : integer := 0;
constant div : integer := 2;
BEGIN
if (clk'event and clk='1') then
CASE currentstate IS
when s1 =>
if (clk < div ) then
clk := clk+1;
else
ctime := ctime + 1;
clk := 0;
end if;
if (darurat = 0) then
M_US <= '1';
M_BT <= '0';
K_US <= '0';
K_BT <= '0';
H_US <= '0';
H_BT <= '1';
end if;
if (mode = '0') and (ctime = 8) and (darurat= '0') then
currentstate <= s2;
ctime := 0;
else if (mode = '1') and (ctime = 4) and (darurat = '0') then
currentstate <= s2;
ctime := 0;
else if (darurat = '1') then
if (ctime mod 2,0) and (wkt_darurat < 4) then
M_US <= '0';
M_BT <= '0';
K_US <= '1';
K_BT <= '1';
H_US <= '0';
H_BT <= '0';
wkt_darurat := wkt_darurat + 1;
else if (ctime mod 2,1) and (wkt_darurat < 4) then
M_US <= '0';
M_BT <= '0';
K_US <= '0';
K_BT <= '0';
H_US <= '0';
H_BT <= '0';
wkt_darurat := wkt_darurat + 1;
else
wkt_darurat := 0;
end if;
currentstate <= s1;
end if;
when s2 =>
if (clk < div ) then
clk := clk+1;
else
ctime := ctime + 1;
clk := 0;
end if;
if (darurat = '0') then
M_US <= '1';
M_BT <= '0';
K_US <= '0';
K_BT <= '1';
H_US <= '0';
H_BT <= '0';
end if;
if (mode = '0') and (ctime = 2) and (darurat = '0') then
currentstate <= s3;
ctime := 0;
else if (mode = '1') and (ctime = 1) and (darurat = '0') then
currentstate <= s3;
ctime := 0;
else if (darurat = '1') then
if (ctime mod 2,0) and (wkt_darurat < 4) then
M_US <= '0';
M_BT <= '0';
K_US <= '1';
K_BT <= '1';
H_US <= '0';
H_BT <= '0';
wkt_darurat := wkt_darurat + 1;
else if (ctime mod 2,1) and (wkt_darurat < 4) then
K_BT <= '0';
K_US <= '0';
wkt_darurat := wkt_darurat + 1;
else
wkt_darurat := 0;
end if;
currentstate <= s2;
end if;
when s3 =>
if (clk < div ) then
clk := clk+1;
else
ctime := ctime + 1;
clk := 0;
end if;
M_US <= '0';
M_BT <= '1';
K_US <= '0';
K_BT <= '0';
H_US <= '1';
H_BT <= '0';
if (mode = '0') and (ctime = 8) and (darurat = '0') then
currentstate <= s4;
ctime := 0;
else if (mode = '1') and (ctime = 4) and (darurat = '0') then
currentstate <= s4;
ctime := 0;
else if (darurat = '1') then
if (ctime mod 2,0) and (wkt_darurat < 4) then
K_BT <= '1';
K_US <= '1';
wkt_darurat := wkt_darurat + 1;
else if (ctime mod 2,1) and (wkt_darurat < 4) then
K_BT <= '0';
K_US <= '0';
wkt_darurat := wkt_darurat + 1;
else
wkt_darurat := 0;
end if;
else
currentstate <= s3;
end if;
when s4 =>
if (clk < div ) then
clk := clk+1;
else
ctime := ctime + 1;
clk := 0;
end if;
M_US <= '0';
M_BT <= '1';
K_US <= '1';
K_BT <= '0';
H_US <= '0';
H_BT <= '0';
if (mode = '0') and (ctime = 2) and (darurat = '0') then
currentstate <= s1;
ctime := 0;
else if (mode = '1') and (ctime = 1) and (darurat = '0') then
currentstate <= s1;
ctime := 0;
else if (darurat = '1') then
if (ctime mod 2,0) and (wkt_darurat < 4) then
K_BT <= '1';
K_US <= '1';
wkt_darurat := wkt_darurat + 1;
else if (ctime mod 2,1) and (wkt_darurat < 4) then
K_BT <= '0';
K_US <= '0';
wkt_darurat := wkt_darurat + 1;
else
wkt_darurat := 0;
end if;
else
currentstate <= s4;
end if;
END CASE;
end if;
END PROCESS;
end behavioral;Error (10500): VHDL syntax error at traffic.vhd(81) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at traffic.vhd(122) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at traffic.vhd(154) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at traffic.vhd(158) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at traffic.vhd(190) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at traffic.vhd(194) near text "CASE"; expecting "if"
Error (10500): VHDL syntax error at traffic.vhd(197) near text "PROCESS"; expecting "if"
